1. Field of the Invention
The present invention relates to methods for forming semiconductor transistors. More particularly, the present invention relates to methods for integrating high-k gate dielectric layers and gate electrodes in the transistor formation process.
2. Description of the Related Art
Designers and semiconductor device manufacturers constantly strive to develop smaller devices from wafers, recognizing that circuits with smaller features generally produce greater speeds and increased packing density, therefore increased net die per wafer (numbers of usable chips produced from a standard semiconductor wafer). To meet these requirements, semiconductor manufacturers have been forced to build new fabrication lines at the next generation process node (gate length).
However, with smaller devices several new problems have surfaced. For example, in the manufacture of Very Large Scale Integrated (VLSI) ultra-submicron technologies, the small technology node sizes require ultra high-k dielectric layers as well as very small gate-to-gate spacing. These structural requirements have in turn created problems preventing full implementation of these process technologies. For example, high-k gate dielectrics are sensitive to the high thermal cycles typically required to activate dopants and repair the damage from implantation steps. In addition, the ultra small spacing between gate electrodes requires heightened efforts in avoiding void formation during the transistor interlayer deposition.
With smaller spaces between adjacent gates, the gap-filing challenges increase dramatically. These challenges result from the tendency of dielectrics formed on a structure having at least one steep sidewall to produce voids from the effect of an overhang. That is, as a dielectric layer such as a primary layer dielectric (PMD) or other interlayer dielectric (ILD) is deposited, given a trench having a large enough aspect ratio, i.e., the height of the trench divided by the width, voids will tend to appear in the deposited dielectric layer. Typically, an overhang will be created at the one of the upper corners of the structure defining the trench.
At some point during the process of depositing the dielectric layer, the dielectric at the level of the overhang thickness from opposing sides of the trench will meet, thus in some cases encapsulating a void in the dielectric. As the spacing between adjacent gates decreases with the decrease in dimensions of the process technology nodes, the adjacent gates will present a trench structure to the interlayer dielectric film when it is deposited.
Much effort in process engineering is required to tune the process to avoid the formation of the void. Preventing void formation typically involves selecting the process parameters to control the overhang thickness relative to the dielectric thickness at the bottom of the sidewall of the trench and controlling the trench width. But the latitude available to the designer to alter the process parameters or the trench dimensions to mitigate void formation problems decreases as process technology nodes decrease in size.
Accordingly, what is needed is an improved process for forming ultra small transistors, one that overcomes the low thermal budgets of the conventional process and its tendencies to produce voids between adjacent gate electrodes.